1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and more specifically to a flash EEPROM (electrically erasable and programmable read-only memory) type nonvolatile semiconductor memory having redundant memory cell rows.
2. Description of Related Art
The flash EEPROM is one of nonvolatile semiconductor memories for which a writing and an erasing can be electrically repeated. This flash EEPROM is configured such that an erasing is limited only to a blanket erasing to a plurality of memory cells, and therefore, can be simplified in comparison with the conventional EEPROM and can be constructed to have a larger storage capacity than that of the conventional EEPROM.
The flash EEPROM is ordinarily constructed so that a memory cell composed of one floating gate transistor stores one bit of data. This memory cell stores the data by utilizing a change of the threshold depending upon the amount of electric charges accumulated in an electrically insulated floating gate. The reading of the data stored in the memory cell is performed by discriminating regardless of whether a current flows between a source and a drain of the floating gate transistor (which constitutes one memory cell, and which will be called a "memory cell transistor" hereinafter), when a predetermined voltage is applied to a control gate of the memory cell transistor.
Adjustment (writing and erasing) of the amount of electric charges accumulated in the floating gate is performed by using a voltage higher than a voltage used at the time of the data reading, so that the electric charge is caused to move between the floating gate and a substrate portion between the source and the drain.
Referring to FIG. 1, there is shown a block diagram of a typical conventional nonvolatile semiconductor memory of this type.
The shown conventional nonvolatile semiconductor memory comprises:
a cell array 1 including a plurality of memory cells MC arranged in the form of a matrix having a plurality of rows and a plurality of columns, and each of the memory cells MC being formed of a floating gate transistor, a plurality of word lines WL each arranged along a corresponding memory cell row and connected to gates of transistors included in the corresponding memory cell row, a plurality of digit lines DL each arranged along a corresponding memory cell column and connected to drains of transistors included in the corresponding memory cell columns, a plurality of source lines SL each arranged along a corresponding memory cell column and connected to sources of transistors included in the corresponding one memory cell columns, the plurality of source lines SL being connected to each other; PA1 a column address buffer 4 and a row address buffer 5 receiving and holding a column address signal ADc and a row address signal ADr an external, respectively; PA1 a row decoder 10x for bringing to a ground potential all the word lines WL of the cell array 1 at the time of an erasing operation where an erase signal EE is active, the row decoder operating, in an operation other than the erasing operation, namely, in a writing operation and in a reading operation, to select one of the plurality of word lines WL in accordance with the row address signal ADr from the row address buffer 5 and to apply to the selected word line a (control gate) voltage selected for a designated operation (ordinarily 12 V in the writing operation and 5 V in the reading operation, assuming that a supply voltage is 5 V); PA1 a source voltage switching circuit 3 for supplying an erase voltage (ordinarily 12 V) to all the source lines SL at the time of the erasing operation, the source voltage switching circuit 3 operating to bring all the source lines SL to the ground potential in the operation other than the erasing operation; PA1 a column selector 12 for selecting one of the plurality of digit lines DL in accordance with the column address signal ADc from the column address buffer 4; PA1 a write/read circuit 13 for supplying to the selected digit line DL a write (drain) voltage (6.about.7 V) corresponding to an input data (Di) in the writing operation where a write signal WE is active, the write/read circuit 13 operating, in the reading operation, to detect and amplify a current flowing the selected digit line DL so as to output an amplified data signal (Do); and PA1 a voltage switch circuit 14x for generating voltages to be supplied to the digit lines DL and the word lines WL in the writing operation and in the reading operation, so as to supplying the generated voltages to the write/read circuit 13 and the row decoder 10x. PA1 a redundant cell array 2 including a redundant memory cell row composed of a plurality of redundant memory cells RMC, each of which is formed a transistor having the same structure as that of the memory cell transistor MC, and which are arranged in all the columns of the cell array 1, a drain and a source of each redundant memory cell RMC being respectively connected to the digit line DL and the source line SL of a corresponding memory cell column, and a redundant word line RWL arranged along the redundant memory cell row and connected to a control gate of the redundant memory cells RMC included in the redundant memory cell row; PA1 a redundant row use flag 6 and a defective row address memory 7, both of a nonvolatile type, respectively for storing data indicative of use of the redundant memory cell row and an address of a row including a defective memory cell, when the defective memory cell is included in the cell array and the redundant memory cell row is to be used in place of the row including a defective memory cell; PA1 a row address comparator 8 for generating an active substitution signal CX when the data stored in the redundant row use flag 6 is indicative of use of the redundant memory cell row and when an address designated by the row address signal ADr is consistent with the address stored in the defective row address memory 7; and PA1 a redundant row decoder 11x operating, in a writing operation or in a reading operation, to supplying to the redundant word line RWL a voltage selected for a designated operation, if the substitution signal CX is active and if the data stored in the redundant row use flag 6 is indicative of use of the redundant memory cell row, the redundant row decoder 11xoperating also operating to supply the ground potential to the redundant word line RWL in the other operation.
In the above mentioned example, all the source lines SL are connected in common, so that the whole of the cell array 1 is erased simultaneously. However, the cell array 1 has a very large storage capacity, the cell array is divided into a plurality of erasing units or blocks each including the memory cells on the order of a few ten thousands bits to a few hundred thousands bits, so that the erasing is performed in units of one block.
To read data stored in the memory cell MS, the source line SL is grounded, a supply voltage is applied to a selected word line and the ground potential is applied to the other non-selected word lines by action of the row decoder 10. In addition, one digit line DL is selected by the column selector 12 so that the current flowing through the selected digit line DL is detected by the write/read circuit 13. In general, when the current is detected, the value "1" is allocated, and when the current is not detected, the value "0" is allocated.
To write data to the memory cell, about 12 V is applied to a selected word line WL (the control gate of the memory cell transistor) by the row decoder 10, and about 7 V is applied from the write/read circuit 13 to a digit line DL (the drain of the memory cell transistor) selected by the column selector 12, so that hot electrons are injected to the floating gate of the selected memory cell transistor. As a result, the threshold of the written memory cell transistor becomes higher than the gate voltage for the reading operation, for example, on the order of 7 V.
The erasing is performed by grounding all the word lines WL and applying a high voltage (on the order of 12 V) to the source lines SL, so that the electrons are extracted from the floating gate of all the memory cell transistors in the cell array 1, by action of the Fowler-Nordheim effect. As a result, the threshold of all the memory cell transistors simultaneously becomes lower than the gate voltage for the reading operation.
In general, since individual memory cells of the flash EEPROM are subjected to small variation in a manufacturing process, the memory cells inevitably have variations in the threshold after the blanket erasure. Since the upper limit of a threshold distribution of the erased memory cells is required to be read out as the value "1", it is necessary to make the gate voltage applied at the time of the reading, as low as possible. On the other hand, a lower limit of the threshold distribution of the erased memory cells have to be not less than 0 V. If there is a memory cell transistor having the after-erase threshold of less than 0 V, the memory cell transistor will allow a current to flow between the source and the drain thereof even if the associated word line is not selected (namely, the associated word line is at the ground potential), with the result that the value "1" is erroneously read out although all the other memory cells connected to the digit line connected to the memory cell transistor in question have a proper threshold. In the writing operation, a leakage current flows through the memory cell transistor in question between the digit line and the ground, with the result that a satisfactory writing characteristics cannot be obtained. In the following, a failure in which the threshold of the memory cell transistor is lower than the ground potential, will be called a "low threshold defect" of the memory cell. In order to minimize the variation of the after-erase threshold of the memory cell transistors so as to avoid generation of the "low threshold defect" of the memory cell, it is necessary to write "0" to all the memory cells before the blanket erase of the flash EEPROM so that the threshold of all the memory cells is brought to about 7 V. This is called a "pre-erase writing".
In semiconductor memories such as RAM having a very large scale array, on the other hand, a defective repairing manner is known to previously prepare a row of redundant memory cells and to replace a memory cell row including a defective ordinarily (namely non-redundant) memory cell, by the row of redundant memory cells. This is very effective in repairing a defective in the memory cell array, in particular, a failure occurring in connection with the word lines, and therefore, in elevating the production yield. In this defective repairing manner, the row of redundant memory cells is formed together with rows of non-redundant memory cells in the same array, so that the digit lines are used in common to the row of redundant memory cells and the rows of non-redundant memory cells, in order to suppress increase of the circuit.
The flash EEPROM is increasing its memory capacity toward a large storage capacity. With microminiaturization of memory cell transistors and enlargement of the cell array area, defective memory cells have appeared, and influence of appearance of the defective memory cells to a cost has become non-negligible. Particularly, in order to repair the defective such as a short-circuiting between adjacent word lines so as to elevate the production yield, it is indispensable to adopt redundant memory cell rows in a word line direction.
Referring to FIG. 2, there is shown an example of the flash EEPROM including redundant memory cell rows in a word line direction. In FIG. 2, elements similar to those shown in FIG. 1 are given the same Reference Numerals, and explanation thereof will be omitted.
The nonvolatile semiconductor memory shown in FIG. 2 is different from the nonvolatile semiconductor memory shown in FIG. 1 in the following points: The nonvolatile semiconductor memory shown in FIG. 2 additionally comprises:
Furthermore, a row decoder 10y, corresponding to the row decoder 10x shown in FIG. 1, operates to ceaselessly maintain at a non-selected level the word line designated by the address stored in the defective row address memory 7 when the data stored in the redundant row use flag 6 is indicative of use of the redundant memory cell row.
In the above mentioned nonvolatile semiconductor memory, since the blanket erase is performed by applying a high voltage to the source lines SL connected to all the memory cells included in an erase unit, the defective memory cell row in the cell array 1 which had been replaced by the redundant memory cell row, and a memory cell row that are never used such as a redundant memory cell row which had not been substituted for the defective memory cell row, are ceaselessly in a non-selected condition, and therefore, are repeatedly subjected to only the erasing operation, without being subjected to even the "pre-erase writing", with the result that the threshold becomes less than 0 V. However, since the drain of these memory cell transistors that are never used is connected to the digit line connected to the memory cell transistors that are used, the reading error and the defective writing as mentioned hereinbefore will occur because of the memory cell causing the "low threshold defect".
In order to avoid the "low threshold defect" of the memory cell, it might be considered to perform the "pre-erase writing", similarly to the memory cell transistors that are used. However, since most of the defective memory cell row which had been replaced by the redundant memory cell row, is a failure in which the memory cell cannot be written, or another failure in which the written condition will disappear abnormally quickly, it is not possible to avoid the "low threshold defect" of the memory cell. As another means for avoiding the "low threshold defect" of the memory cell, it might be considered to divide the source lines of the memory cell transistors in units of row, so that at the time of the blanket erase, a high voltage is never applied to the source of the memory cell transistors that are never used, for the purpose of preventing the lowering of the threshold. However, the division of the source lines will inevitably result in an increased cell array area, and therefore, in an increased cost. Accordingly, this is not practical.